Years of Experience
3-5 Years

Job Description

• Candidate should have very good experience in complete PnR and Signoff tasks including Floor planning, Placement, CTS, routing, post route optimization, STA closure, Physical verification and power analysis.
• Candidate should have worked in multiple Tapeouts. The experience in 16nm and lower nodes is an added advantage.
• Candidate should have good knowledge in scripting languages like TCL and PERL.
• Candidate will be responsible for executing PNR tasks of the blocks and or full chip activities and also he needs to help couple of junior members in the team whenever they need some help.

Years of Experience
5-12 Years

Job Description

• Candidate should have very good experience in complete PnR and Signoff tasks including Floor planning, Placement, CTS, routing, post route optimization, STA closure, Physical verification and power analysis.
• Candidate should have worked in multiple Tapeouts. The experience in 16nm and lower nodes is an added advantage.
• Candidate should have good knowledge in scripting languages like TCL and PERL.
• Candidate will be responsible for executing PNR tasks of the blocks and or full chip activities and also he needs to help couple of junior members in the team whenever they need some help.
• We have technical and Managerial ladder for the candidates and as an organization we will help the candidate to identity and grow either in technical ladder or Managerial ladder based on the candidates skill set and the interest.
• Candidates also will have flexibility to change the ladder later.

Years of Experience
3-5 Years

Job Description

• Candidate should have very good experience in complete STA Signoff activities including Timing and noise analysis.
• Candidate should have worked in multiple Tapeouts. The experience in 16nm and lower nodes is an added advantage.
• Candidate should have good experience in constraint development and debugging.
• Experience in lower power sign off is an added advantage.
• Candidate should have good knowledge in scripting languages like TCL and PERL.
• Complete understanding of Synthesis/STA concepts (Synthesis, Timing, Equivalence Checks, Extraction, Noise, Power, UPF/CPF) and various flow
• Understanding Test/DFT modes SDC
• Familiarity with PD concepts/flow and assist PD team if and when required
• Interact with Frontend, PD, DFT team to communicate work progress and closure

Years of Experience
5-12 Years

Job Description

• Familiarity with PD concepts/flow and assist PD team if and when required
• Own full chip responsibilities
• Interact with Frontend, PD, DFT team to communicate work progress and closure
• Interact with tool vendors and debug tool related or IP related issues independently
• Have foresight into execution. Create risk mitigation plan (RMP)
• Participate in different project reviews. Conduct team meeting regularly
• Generate/collect feedback from team members on project/tasks flow and initiate correction/improvement in methodology
• Participate in Focal process

Years of Experience
6-12 Years

Job Description

• Complete understanding of DFT concepts and flow (scan/ATPG/Memory BIST/ Bscan, Vtran/Simutest)
• Develop/Plan complete DFT/test strategy for the device as per SOW
• Create DFT implementation plan, delegate to team members and tracking
• Test mode timing support/debug and closure at full chip level
• Handle post-silicon pattern generation, Validation and ATE debug/support
• DFT specification creation
• Complete familiarity of tools used in DFT implementation (DC/RC, Tk/Tmax, Virage/Mentor memory BIST, Mentor Bscan) with expertise in one of them
• Independently handle IP verification strategy and implement and verify the same
• Good exposure to STA tool. Assist STA team in timing closure for DFT modes
• Good scripting skills (TCL/Perl)
• Familiarity with PD concepts/flow and assist PD team if and when required
• Own full chip responsibilities
• Interact with DM/FM, STA/PD/test/qual/customer team to communicate work progress and closure
• Interact with tool vendors and debug tool related or IP related issues independently
• Have foresight into execution. Create risk mitigation plan (RMP)
• Participate in different project reviews. Conduct team meeting regularly
• Generate/collect feedback from team members on project/tasks flow and initiate correction/improvement in methodology
• Participate in Focal process

Years of Experience
5-10 Years

Job Description

• Hands on experience with leading Physical Verification activities at full chip level in multimillion gate SoC designs in cutting edge process technologies (40nm, 28nm, 16nm, 10nm)
• Lead PV activities on SoC designs with expertise in DRC, LVS, DFM, HV checks and cleanup
• Expertise in running PV checks on Flat/Hierarchical SoC designs with multiple power domains
• Excellent understanding of DPT, DFM , DFY, Fullchip checks in lower technology nodes
• Work closely with PD team to define methodology to address PV issues during PnR
• Work closely with CAD teams and involve in methodology development and improvement
• Own SoC PV activities while managing a team of 5-10 engineers

Desired Skills & Experience:

• Strong knowledge of physical verification flows and methodology.
• Knowledge of all aspects of ASIC physical design.
• Experienced in industry standard tools used for physical verification such as Synopsys ICV, Mentor Calibre, etc.
• Multiple tapeouts experience with a track record of successful signoff.
• Layout design background and experience a plus.
• Strong scripting skills using Perl, TCL, other scripting languages to debug flow related issues and make enhancements as appropriate.
• Excellent verbal and written communication skills are required.
• Excellent interpersonal and analytical skills with the ability to work independently.

Years of Experience
3-8 Years

Job Description

• B.E/B.Tech/M.E/M.Tech or PhD in Electronics or Electrical Engineering with relevant professional experience in mixed signal CMOS circuit design
• Strong knowledge of Analog integrated circuit design fundamentals on sub-micron CMOS processes, including knowledge of low geometry physical design constraints and issues
• Experience designing low-power / high-performance Analog building blocks with industry standard design tools
• Good working knowledge of CMOS technology

Product knowledge in the following areas:

• Analog and Digital Circuit Design in the following areas;
• Power Management: LDO, DC DC Converter, Charge Pump, BGR, Temp. Sensor etc.
• Clock Circuits: PLL, Oscillator, Clock Generator, DLL etc.
• Data Converters: SAR/ SD/ Pipeline ADC, DAC, Signal Processing, Filters
• IO, SERDES and PHY: LVDS/ USB/ PCIe/ HDMI PHY, SERDES and IO
• Able to work independently on block level implementation and verification
• Strong numerical and analytical skills including an understanding of signal processing and analysis techniques, including DSP and/or analog filter design
• Experience in floor-planning and supervision of circuit layout at the cell level
• Lab and silicon validation experience
• Working with various teams to define requirements (modelling, packaging, hardware, DFT and ESD)
• Experience with mixed signal modelling and verification (using C, Matlab or Verilog-A/AMS, Wreal)
• Familiarity with Analog system modelling techniques and related accuracy trade-offs
• Proficient in circuit analysis, system theory and stability criteria
• Understanding of Chip level floor-planning constraints and trade-offs
• Minimum of 5 years industrial experience working in Analog or Mixed signal IC design
• Proven experience of taking designs from concept to mass production with understanding of issues related to design for manufacture and production test
• Good interpersonal skills, share technical expertise and knowledge, contribute to design reviews, work effectively to resolve conflicts
• Strong written and verbal communication skills

Years of Experience
3-8 Years

Job Description

• Candidate should have good exposure of analog layout concepts like matching, shielding etc.
• The selected candidate will work on floorplan, Layout and verification(DRC/LVS) of various analog and mixed signal blocks like amplifiers, references, regulators (LDO/DCDC – Buck, Boost, Multiphase), PLL, ADC, DAC across a wide range of technologies from scratch.
• Will have to interact with design teams to ensure on time meeting all the design requirement.
• Must be technically independent, and able to work in a multi-site team environment.
• Strong verbal & written communication skills are desired

Years of Experience
3-5 Years

Job Description

• B.E/B.Tech/M.E/M.Tech or PhD in Electronics or Electrical Engineering with relevant professional experience in mixed signal CMOS circuit design
• Basic knowledge of Analog integrated circuit.
• Good understanding of Verilog-A/AMS/Wreal modelling.
• Understanding mixed signal verification environments and connect modules
• Understanding on simulators and verification tools.
• Develop efficient and reusable state of the art verification test benches
• Able to work independently on block level verification and modelling
• Good interpersonal skills, share technical expertise and knowledge, contribute to design reviews, work effectively to resolve conflicts
• Strong written and verbal communication skills
• Knowledge of UVM-AMS is a plus

Years of Experience
3-8 Years

Job Description

• Good in LTE Protocol Stack Development
• MAC, RLC, PDCP, RRC, NAS Stack Development
• Very good in Linux OS concepts like Process, thread, Memory Management, IPC, Kernel, Timers etc
• Very good in C/C++ and programming with IPC
• Hands on experience in cdb/gdb, unit testing, build and run
• Good knowledge of RRC Messages/Call flows and IE’s
• Good Knowledge of NAS Messages/Call flows and IE’s
• Good knowledge of Inter-RAT Handover with GSM/UMTS network
• Knowlledge of CDMA Call flow is a plus
• Knowledgeable in CarrierAggregation, Dual Connectivity, eICIC, eMBMS advantage

In case of lead should have developed a PoC in LTE either in UE or eNB

1. You will be developing some modules of 3GPP RAN either in UE/modem or in eNB. 3GPP specification knowledge is required in L1 or L2/L3 stack.
2. He should have very good knowledge, 5 years experience in NAS/RRC/PDCP/RLC/MAC and PHY layer software implementation and inter stack communication.
3. He should have implemented some modules upto at least 3GPP Rel-10 and should have knowledge in Rel-11/12/13/14.
4. Good knowledge in RRC ASN.1 messages, NAS Messages and MAC – DCI messages.
5. Should have 5+ years experience in C/C++ programming in Linux environment.
6. Should have good OS Kernel/Memory/Scheduling concepts with multi-threading and multi-process environment programming.
7. Should have good experience with IPC – Semaphore/mutex, MessageQueue, Buffers, Shared Memory and Timer implementations.
8. Should have good knowledge of Socket programming.
9. Should be ready to work in both Bangalore and Hyderabad locations as our projects require.

Years of Experience
2-6 Years

Job Description

• Good in LTE Protocol Stack Testing
• PHY, MAC, RLC, PDCP, RRC, NAS Stack Testing
• Protocol Conformance Testing, 3GPP-36.523 or GCF/PTCRB
• Python Automation Test Scripting
• Lab test – Sanity Test, Functional Test, Field Test
• Log Analysis – Bug Finding and Troubleshooting
• Specification Conformance Test Case Writing
• Good knowledge of RRC Messages/Call flows and IE’s
• Good Knowledge of NAS Messages/Call flows and IE’s
• Good knowledge of Inter-RAT Handover with GSM/UMTS network
• Knowledge of CDMA Call flow is a plus
• Knowledgeable in LTE-Adv like CarrierAggregation, Dual Connectivity, eICIC, eMBMS advantage
• Dual SIM Card begaviour Testing
• In case of a Lead- Should have Python Testing Scripting

Years of Experience
1-3 Years

Job Description

• QA automation framework experience
• C/C++ or Python, linux multi-threading concepts, parsing and implementation, gdb/linux debugging skills,
• Experience of doing E2E multimedia testing (lab and field) on Android OS amd debug.
• Has LTE testing experience to understand the flow of activities.
• RRC/MAC knowledge in LTE Access stratum is a plus.
• Has worked actively on Perl/Python programming.
• GIT Build, integration, release and platform bring up. Exposure with Jenkin and its integration is plus
• Test plan, test case design, script development, test execution and reporting

Years of Experience
3-8 Years

Job Description

• Total 2-5 years of experience and above in software development, integration and testing
• Experience in integration and testing
• Excellent problem solving and troubleshooting & debugging skills
• Excellent analytical skill and critical thinking.

Programming/Scripting/OS Skills (mandatory)

• Good programing skills in Python and knowledge of OOPs concepts.

Experience in any one of the technical areas as stated below (Either of A/B or both)

1. Networking/SDN
   1. 1 year or more development experience in Networking (Switching, SDN)
   2. Hands on experience in networking – Switching, DPDK, Network Switches, SDN
   3. Knowledge on Open Network Linux (ONL), SDN control like ONOS, ODL, Open switch Specification is highly desirable
2. Data Centre/Virtualization/Cloud (Any 2 or more are mandatory)
   1. 1 year or more development experience in Data Center cloud architecture, Virtualization and orchestration and different orchestration tools.
   2. Has in depth of knowledge of the Open Source components, Open Stack, cloud management, Docker containers, Kubernetes.
   3. Familiarity with High Availability (HA) & Scalability

Years of Experience
3-8 Years

Job Description
A Senior Engineer is primarily responsible for the following:

Projects

• Understand high level requirements and customer’s inputs and contribute towards the detailed feature level requirements. Active participation in design by brainstorming and considering multiple design options during design.
• Design, development and testing of module(s) as per the requirements.
• Ability to analyse and debug technical issues with minimal guidance from the senior team members.
• Contributes in feature estimations to help develop the release plan
• Active participation in the quality practices in the project like code and artifact reviews, static and dynamic code analysis, code coverage, defect removal etc.

Experience

• Overall 3-5 years in design and development
• Exposure to contemporary software engineering methods and processes

Know How

• Must have: Knowledge and hands-on experience in LTE technology
• Hands-on experience in LTE Core Network elements (MME, SGW, PGW)
• Knowledge of 5G network is a plus
• Has strong hands-on experience in C programming language
• Development and testing in Unix/Linux environment
• Knowledge of development and debugging tools required – Wireshark, gdb, gcc, other static/dynamic code analysis tools
• Knowledge on multi-thread programming preferred
• Exposure to Agile methodologies in software development is a plus
• Exposure to configuration management tools such as Clearcase / Git

Years of Experience
8-15 Years

Job Description

• Act as Functional Safety Manager for Powertrain products
• Perform safety management activities according to relevant standards during all project phases (e.g. FMEDA, qualitative and quantitative fault tree analysis)

• Review safety architectures and safety plans to ensure compliance with ISO26262
• Conduct reviews with product teams to ensure functional safety standards are being met
• Cascade safety requirements to the systems, subsystems, and component levels in product portfolio.
• Lead and coordinate creation of functional safety documentation according ISO26262
• Coach team on best practice and create Functional Safety awareness across departments
• Prioritize Functional safety activities to ensure project maturity

Profile:

• Detailed knowledge and proven experience with ISO 26262 for >6 years in automotive industry.
• Knowledge of general Functional Safety Theory
• Experience in Software Quality and process ( e.g., SPICE, CMMI )
• Experience with Products Development Life Cycle (Systems, Software)
• Proven record of taking customer requirements from design to production
• engineering degree (industrial, electromechanical or mechanical)
• Experience in powertrain technologies (vehicle dynamics, transmissions, engines, motors, Brake system, high voltage unit)
• Experience with system engineering approaches (requirements engineering / management, functional analysis and allocation, architecture design, validation and verification)
• You are familiar with automotive development and quality process (FMEA/FTA methods/tools)
• The ability to communicate complex ideas succinctly and persuasively to peers, management and customers

Years of Experience
10-18 Years

Location
Germany

Tasks & Responsibilities

• SW project management with focus on activities of external software suppliers for the implementation of new car functions (Car Infotainment, Headup-Displays, ADAS, instrument cluster, others)
• Supplier performance development to improve delivery quality, development- and cost efficiency
• Cooperation with the department of System Engineering, SW integration team and SW development teams
• Coordination of activities with system testing and quality department
• Handling of internal management tasks in software development as needed
• Reporting status and progress of activities and projects

Requirements

• Experience in the management of international and distributed software development projects (embedded SW development), preferably in the automotive sector
• Good knowledge and experience in the fields of car infotainment, instrument cluster or ADAS
• Knowledge and experience in supplier management are a plus
• Good knowledge of engineering development processes (SPICE, CMMI)
• Good communication skills, strong own initiative and analytical skills
• Reliability and flexibility, willing to travel
• Fluent in English (speaking, reading and writing), German is a plus

Years of Experience
1-3 Years

Job Description

• QA automation framework experience
• C/C++ or Python, linux multi-threading concepts, parsing and implementation, gdb/linux debugging skills,
• Experience of doing E2E multimedia testing (lab and field) on Android OS amd debug.
• Has LTE testing experience to understand the flow of activities.
• RRC/MAC knowledge in LTE Access stratum is a plus.
• Has worked actively on Perl/Python programming.
• GIT Build, integration, release and platform bring up. Exposure with Jenkin and its integration is plus
• Test plan, test case design, script development, test execution and reporting