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Join the Team

    • 3+ years of experience in Physical Design for 14nm or less technology

    • Responsible for block level STA/timing closure / PNR.

    • Well versed with Synopsys Prime Time or Cadence Tempus or equivalent timing closure tool

    • Good communication skills English

    • 3+ years of experience in developing and supporting design for test (DFT) structures.

    • Determine design for test approaches and develops DFT architecture. Design and verify DFT structures for memories (MBIST), digital and analog circuitry.

    • Performs scan synthesis. Creates, simulates and verifies automatic generated test patterns (ATPG). Creates functional tests and corresponding test patterns.

    • Good communication skills English

    • Strong SV & UVM skills 

    • Good knowledge in any of the protocols like Ethernet/PCIE/USB/DDR/AXI/SATA/MIPI 

    • Experienced in developing test bench components, writing tests and coverage tuning 

    • Digital Design and Verification Verilog/System-verilog 

    • Good scripting knowledge using perl / python

    • Good communication skills English

    • Work independently on block level and chip level Analog layout designs, coordinating with circuit designers and layout leads.

    • Proficient in FinFET layouts 

    • Custom layout experience in high-frequency circuits such as LNAs, BBF, BIAS, Mixers, VCOs, DAC, ADC, PLL, LDO, etc.

    • Familiarity with Cadence-Virtuoso, PVS, ASSURA, and Calibre tools.

    • Ability to effectively work and communicate with global engineering teams.

    • Good communication skills English

    • Experience in designing of analog blocks for power-management like LDO, BGR, UVLO, Charge-pump, Osc, Gate Drivers etc.

    • Strong communication skills & team player

    • Strong knowledge in analog circuit design & simulations

    • Good knowledge of Analog layout concepts and able to guide layout team with layout constraints

    • Hands-on experience in Cadence's tool flow

    • Good communication skills English

    • Experience in mixed-signal verification of chip

    • Experience with mixed signal / co-simulation (analog, digital) verification methodologies

    • Experience writing verification plans, creating test benches and automating regression test suites, preparing and presenting detailed verification reviews

    • Experience developing behavioral models for analog IPs in WREAL, Verilog-AMS

    • Understand and debug digital RTL and analog schematics

    • Working knowledge of state-of-the-art EDA tools: Cadence Virtuoso, Cadence Incisiv/Xcelium, Cadence Vmanager

    • Strong background in verification languages and methodologies (e.g. Verilog, SystemVerilog, UVM, SVA).

    • Experience in configuration database management

    • Good communication skills English

Actively hiring for the following roles

Apply Now to Join Cientra

​Cientra is an Indian multi-national product solutions company incorporated in the USA and Germany.

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