Automotive software development, engineering and technology services

SoC/IP RTL Design Offerings

Cientra team has extensive experience with several complicated projects and flows, including UPF development, static checks, design for PPA and trade-offs, and DFT and DFV needs.

RTL Design

Cientra has extensive and in-depth demonstratable expertise in several facets of the RTL / SoC design in the areas of networking, processor, multimedia, mobile, and automotive sectors.

Our specialists with decades of hands-on experience, an internally developed IP portfolio, and detailed exposure to TFM (Tools, flows, and methodologies) across the industry, enable our customers to a faster and more predictable time to market (TTM) and quality deliverables. The in-house processes which are in line with most of the industry standard practices, make Cientra one of the unique providers of RTL design solutions provider for the semiconductor industry.

Our RTL design team has done and is capable of putting together system requirements, architecture definition, micro-architecture spec, RTL design, and sanity test, various tool collateral creations, design checks and compliance using industry-standard tools and handing over the collaterals to the various stakeholders in Verification, DFT and Physical implementation teams. The capability is not only restricted to IP design but also extends to subsystem or SoC design and integration. Cientra team having worked with multiple Tier 1 customers, has great exposure to many complex projects and flows in UPF creation, static checks, design for PPA and trade-offs, DFT and DFV requirements.


  • IP/SoC Design and Netlist delivery
  • Front-end design of complex multi-clock, power domain blocks, and low-power designs
  • RTL Signoff checks like Lint/, CDC (Clock domain crossing), FEC (Formal Equivalence Checks),  Synthesis (logical/physical aware)
  • Knowledge of Verification Methodologies to actively participate in Debug Analysis
  • Knowledge of Synthesis, static timing analysis, and physical design flows
  • Microarchitecture development (block specifications, development plan, and architecture from the top-level digital features/functionality of the chip)
  • Proficient in any of the category IPs and SoCs :
    • Slow peripheral like I2C, UART, SPI, SM Bus, PM Bus
    • Fast Peripherals like PCIe, Ethernet, USB, etc
    • Infrastructure components in GPIO, Bus Bridges, SoC interconnect, Subsystem / SoC bus architectures, AMBA Bus Interfaces like APB, AHB, AXI
    • CPU Design – RISC-V, Power PC, ARM CPUs, Cache Controllers, MMU, IO-Coherency, Fast ALUs, MACs
    • DSP IPs like FFT, FM ModulatorClock, and Reset generators for SoC / Subsystems
  • Power optimizations and standards
  • SoC integration
Slow Peripheral IP
Some of the Slow Peripheral IP modules developed by Cientra are:


  • UART
  • I2CM
  • I2CS
  • SPIM
  • SPIS
  • CANM
  • CANS
  • SMBusM
  • SMBusS
  • PMBusM
  • PMBusS
  • I3CM
  • I3CS
  • I2SM
  • I2SS
Infrastructure Component
  • GPIO
  • Timer
  • Interrupt Ctrl
  • RCC
  • AES -128
  • SHA – 256
  • 10/100/1G Auto Neg
  • PRBS
  • RS – 8 FEC Engine
  • Hamming ECC
  • Encoder/Decoder 8B/10B
  • RTC(Real Time Clock with APB)
  • IPV4 Checksum
  • 128B/130B Encoder/Decoder
  • DSI(Display Serial Interface)
  • Camera Serial Interface(CSI)
  • FM Modulator
  • FFT
  • Baugh-wooley Multiplier
  • Wallace tree Multiplier
  • FM Demodulator
  • LZW Compression Algorithm
CPU Component
  • 8051
  • NIC
  • TBU
  • DDR3/DDR4/DDR5 Controller with DFI 4.0
Bus Interface
  • AHB2APB Bridge
  • AHB Arbiter
  • DMA Controller
  • AXI2AHB Bridge
  • Speed Connect NOC
  • Tlink-UH to AXI
  • Tlink-UL to APB
  • AXI Bridge(Master and Slave)
  • AXI Fabric
  • Scatter gather DMA
  • AXI2APB Bridge
  • AXI2AHB Bridge
  • LPC Interface Master
  • LPC Interface Slave
  • AXI2AXI Bridge
Fast Perph IP
  • Pause Frame Generator
  • RMON
  • Gigabit MAC
  • LTSSM for USB and PCIE
  • USB 3.0
  • xHCI
  • MG MAC


RTL signoff consists of delivering the various collaterals to the stakeholders in DFT, Verification, and Physical design team, As the RTL implementation progresses, the sign-off checks are run continuously to ensure good quality RTL is being provided downstream on a regular basis for the various stakeholders to successfully move forward. Cientra follows its own well-defined milestone definitions, measurement metric, and SLAs (Service level agreements to fix issues) to ensure quality and timely deliverables to the stakeholders.


Examples of RTL Signoff requirements include:

  • PPA + Schedule dashboard – Plan vs Actual
  • Every milestone release is sanity clean, Lint clean, CDC clean, synthesis elab clean and open issues document
  • Collateral release in Register Description formats in IP-XACT XML format, timing constraints, UPF, DFT constraints, etc

Talk To Us

15 + 15 =