Design Verification capabilities

With Cientra’ s large verification team across various customers and diverse projects, it has an exceptional proficiency in various verification or technology domains. Cientra’ works with multiple Fortune 500 semiconductor companies to deliver their projects and has executed multiple projects in different engagement modes across multiple domains. Cientra has expertise in the IP, subsystems and SoC level verification using SV/UVM, Formal Verification, GLS. The various domains Cientra has a strong know-how are CPU Cache coherency, High & Low speed peripheral IPs (MAC+PHY), and Wireless technologies. Cientra has a verification methodology which can seamlessly work at IP, Subsystem and SoC level.

The verification capabilities brief is described below:

• Verification planning with each milestone definition
• Feature extraction, functional coverage model development
• Integration of third-party VIPs for a TB creation
• SV / UVM TB development
• Register abstraction based (RAL) flow enabling design and verification reuse
• Assertion-based verification using SVA
• Test case development with Functional and code coverage closure
• Formal verification techniques, if required, for selective verification effort
• Verification VIP developments
• Regression management
• FPGA prototyping, emulation platforms, and system demonstrators
• Low-power verification techniques – power estimation, CPF/UPF
• Gate level simulation
• Functional Test vector generation for Post Si test
• Development of power virus vector, if required

We understand, how critical it is to find the right Semiconductor solutions partner, and also, wrong decision-making can be expensive.To know our distinctive qualities in comparison to other Semiconductor design companies, kindly email us at info@cientra.com

Explore our RTL design offerings