DOMAINS

Digital Signal Processing (DSP) Design Solutions

The ever growing demand for bigger, more powerful and discrete systems is growing day by day. Product companies are looking to maximize performance and minimize size. They are constantly on the lookout for more efficient ways to reduce power consumption, while improving performance on an ever-shrinking chip – all the while trying to stay ahead in a rapidly-evolving ecosystem.

OVERVIEW OF

Digital Signal Processing Design & Development

(our offerings include SoC, ASIC, FPGA, DFT, RTL & IP design)

Time and again Cientra has innovated to build efficient digital systems. Our expertise allows us to partners quickly build innovative architectures and systems on a chip. we have been able to rapidly turn around highly robust and functional systems on the smallest of silicon wafers, with the most stringent power requirements – all this owing to our domain expertise in SoCs, ASICs, FPGA to ASIC conversion.

Our Digital Design Group:

Possess top system level expertise to quickly integrate customer’s vision into an ASIC-based solution
Specializes in high speed, high reliability, and low power designs
Owns capabilities in various design and verification languages, tools and methodologies that are integral to achieving successful, affordable
System-on-Chip (SoC) solutions
Has proven expertise on cutting edge EDA tools and the latest FinFET nodes

ASIC / FPGA Design Development

Micro Architectures
Develop micro architecture for SoC & Sub systems for various domains like networking, cell phone, IoT, Server, audio video, wireless

RTL & IP Designs
RTL implementation at IP, sub system, SoC level with Verilog, VHDL, System veri

Lint, CDC
Clock domain cross checks, Linting checks using tools like Spyglass

SoC Analog & Digital IP Integration
Analog blocks with digital integrated solutions

Synthesis, STA, LEC
Synthesis & Static timing analysis with optimization on area and speed, Logic equivalence checks and formality checks

Design Verification

IP Level functional verification
Functional coverage & assertion driven random verification on varieties of IP’s like on internal and external bus protocols, CPU’s, Audio, video protocols, wireless protocols

ARM based CPU & Power aware verification
ARM processor / X86 based verification with HW-Firmware with ISR’s and low power CPF/UPF based simulations

SoC & full chip level verification
Building SoC verification framework and porting existing environment and testing for usecase, bench mark testing, performance

Gate level simulations & Automation
Gate level simulations at pre and post netlist with SDF and test automation

Emulation & Post Silicon Validation

Multi Emulation Platform
Design testing on Emulation platforms like Zebu, Palladium, Veloce, HAPS and FPGA prototype of design.

Performance, System level testing
Bench marking tests, performance and system level test development and validation

Pre & Post silicon FPGA board
Bring up and testing of functionality and chip characteristics

Physical Design

Early stage partnership
Technology node selection, flow development, tools selection, tool evaluation, die-size estimation and optimization

Synthesis
Logical and physical Synthesis, low power synthesis, flow development, constraint development and validation

Block level PnR implementation and Signoff
Floor planning, PnR, PPA improvement, low power implementation and signoff

Fullchip PnR, Chip assembly and Signoff
Die size reduction, power reduction, IO ring creation, bump planning, bump optimization, bump signoff with packaging team, partioning, power planning, fullchip integration, analog integration, analog custom routing, cts, routing, post route optimization, STA and noise closure, STA constraint development and Physical verification signoff

Tapeout and post tapeout support
Tapeout to the foundry , Job view review, FIB support, Metal revision with minimum number of metal layers

DFT

ATPG and validation
ATPG vector generation, pattern validation BIST vector generation and verification

Test program development and Test time reduction
Test program planning and development to meet the coverage, test time budget and Test time reduction

Silicon bring up and Tester Support
Silcon bring up support, pattern failure debug and DPM improvement

We understand, how critical it is to find the right Digital Signal Processing Design Solutions partner, and also, a wrong decision-making can be expensive.

To know how we are different from other Digital Signal Design solution companies, please email us at info@cientra.com.