Semiconductor Engineering, Design, & Development Solutions

The Integrated Circuit (IC)/ ASIC wing of Cientra works on the principle of redefining the boundaries of innovation, especially in the development of silicon chips. Our semiconductor design solutions include RTL design, design verification, physical design, and analog layout offering – and also provide RTL to GDSII value offerings. We do this with the primary goal of helping technology companies monetize their expertise.

Analog

Priding in 250+ person years of experience across the service line.

Digital

Building innovative architectures and systems on a chip

OUR Semiconductor Solutions

Semiconductor Design

As a domain expert, Semiconductor companies rely on our expansive experience of over 250 person-years to go from Silicon to System. Our technological solutions have helped businesses across the Mobile, Consumer, Automotive, Aviation, and Industrial sectors. Combining an entrepreneurial zeal and extensive knowledge, Cientra has provided complete tech solutions in the Digital, Analog and Mixed Signal, and Embedded Software space – also setting high standards in the area of microelectronics.

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Developing feature-rich chipsets

From design to architecture, team Cientra is adept at developing, testing, and validating materials used.

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Setting up an ecosystem

We help our partners setup a complete support system around their new product by institutionalizing industry-recognized processes. Our analog and mixed signal skills cover the entire spectrum – from design to GDSII and physical validation.

Analog and Mixed Signal Design

In a highly digital environment, we believe that systems need to talk to each other and the outside world. These connections require analog components.

Our extensive experience in developing components across domains such as Power Management, Data Converters, Clock Circuits, and high-speed Communication Interfaces has made us the preferred solution provider for global leading enterprises. We can ramp up high-speed analog blocks or a low power and area-constrained design as well as reduce full chip level simulation time by creating accurate Analog models at the block and full chip levels.

Our AMS (Analog Mixed Signal) Design Solutions include:

Architecture planning and feasibility Analysis
Circuit design and simulations
Layout design and Verification
Performance and Functional Modeling
Mixed Signal Verification and Co-Simulation
Design and Layout Migrations
Engineering Sample validation

Power Management

At Cientra, we have rich experience working across domains of Power Management Circuit and the necessary frameworks for low turn-on voltage circuits. We have successfully delivered a variety of regulators, references, protection circuits, and temperature sensors, in addition to high efficiency and low EMI noise. Some of the Power Management modules designed by Cientra are listed below:

DC-DC Converters (Buck/Boost)
Li-Ion Chargers
Switched Capacitor Voltage Regulator
Charge Pump
MOSFET Drivers
Motor Driver
LDOs
Low Power POR/BOD
High Precision BGRs
High Precision Temperature Sensor
Constant Current Sink-LED Driver

Clock Circuits

Various circuits for clock generation and synthesis – including XO and VCXO clock modules, PLL based clock generators – designed at Cientra cater to state-of-the-art medium frequency range applications. These circuits provide precise clocks to the required areas of the chip. We also have proven capabilities in designing high-performance low skew DLLs for different applications e.g. clock management, BIST, etc Some of the Clock Modules designed by Cientra team are:

Low Power Crystal Oscillator, RC Oscillator
Low Jitter PLL and DLL Designs
Clock Buffers and Dividers

Signal Processing

At Cientra, we have delivered various Data Converter designs supporting low voltage and wide supply voltages; and have a proven record in designing ADCs with programmable resolution. We also have experience in delivering low-noise and sensor interface applications. Some of the Data Converter Modules designed by Cientra are mentioned below:

SAR, Sigma Delta, and Pipeline ADCs
DAC with high speed, low power, and a rail-to-rail buffer
Read Out ICs for Accelerometers
Filters

High Speed Interfaces

We have a credible reputation in the part/ complete design of the following high speed blocks:

LVDS and CML Drivers
USB 2.0/3.0, PCIe Gen 2/3
Server Interconnect 10/11.2 Gbps
General Purpose IO Library
High Speed SERDES at 5 -12 Gbps
PHY Porting: MIPI, USB, HDMI, PCIe, DDR etc.

Technology Migration

Whether you are looking for some support in area reduction/feature enhancements or migration of your existing IP libraries from one technology to another, Cientra can assist you with the following services:

Porting design from the same node of one FAB to another
Porting design from same FAB but different node
Feature enhancement or removal etc.

VLSI Design

The ever-growing demand for bigger, more powerful, and discrete systems is growing day by day. Product companies are looking to maximize performance and minimize size. They are constantly on the lookout for more efficient ways to reduce power consumption, while improving performance on an ever-shrinking chip – all the while trying to stay ahead in a rapidly-evolving ecosystem.

Time and again Cientra has innovated to build efficient digital systems. Our expertise allows us to partner quickly to build innovative architectures and systems on a chip. we have been able to rapidly turn around highly robust and functional systems on the smallest of silicon wafers, with the most stringent power requirements – all this owing to our domain expertise in SoCs, ASICs, and FPGA to ASIC conversion.

Our Digital Design Group:

Possesses top system-level expertise to quickly integrate customer’s vision into an ASIC-based solution
Specializes in high speed, high reliability, and low power designs
Owns capabilities in various design and verification languages, tools, and methodologies that are integral to achieving successful, affordable
System-on-Chip (SoC) solutions
Has proven expertise in cutting-edge EDA tools and the latest FinFET nodes

ASIC / FPGA Design Development

Micro Architectures Develop micro architecture for SoC & Sub systems for various domains like networking, cell phone, IoT, Server, audio video, wireless RTL & IP Designs RTL implementation at IP, sub system, SoC level with Verilog, VHDL, System veri Lint, CDC Clock domain cross checks, Linting checks using tools like Spyglass SoC Analog & Digital IP Integration Analog blocks with digital integrated solutions Synthesis, STA, LEC Synthesis & Static timing analysis with optimization on area and speed, Logic equivalence checks and formality checks

Design Verification

IP Level functional verification Functional coverage & assertion driven random verification on varieties of IP’s like on internal and external bus protocols, CPU’s, Audio, video protocols, wireless protocols ARM based CPU & Power aware verification ARM processor / X86 based verification with HW-Firmware with ISR’s and low power CPF/UPF based simulations SoC & full chip level verification Building SoC verification framework and porting existing environment and testing for usecase, bench mark testing, performance Gate level simulations & Automation Gate level simulations at pre and post netlist with SDF and test automation

Physical Design

Early stage partnership Technology node selection, flow development, tools selection, tool evaluation, die-size estimation and optimization Synthesis Logical and physical Synthesis, low power synthesis, flow development, constraint development and validation Block level PnR implementation and Signoff Floor planning, PnR, PPA improvement, low power implementation and signoff Fullchip PnR, Chip assembly and Signoff Die size reduction, power reduction, IO ring creation, bump planning, bump optimization, bump signoff with packaging team, partioning, power planning, fullchip integration, analog integration, analog custom routing, cts, routing, post route optimization, STA and noise closure, STA constraint development and Physical verification signoff Tapeout and post tapeout support Tapeout to the foundry , Job view review, FIB support, Metal revision with minimum number of metal layers

DFT

ATPG and validation ATPG vector generation, pattern validation BIST vector generation and verification Test program development and Test time reduction Test program planning and development to meet the coverage, test time budget and Test time reduction Silicon bring up and Tester Support Silcon bring up support, pattern failure debug and DPM improvement

Emulation & Post Silicon Validation

Multi Emulation Platform Design testing on Emulation platforms like Zebu, Palladium, Veloce, HAPS and FPGA prototype of design. Performance, System level testing Bench marking tests, performance and system level test development and validation Pre & Post silicon FPGA board Bring up and testing of functionality and chip characteristics

We understand, how critical it is to find the right Semiconductor design solutions partner, and also, wrong decision-making can be expensive.

Cientra has offices in India (Bangalore, Hyderabad, and Noida), the USA, and Germany.

To know how we are different from other Semiconductor design companies, please email us at info@cientra.com.