CASE STUDY

Implemented chip and block level physical design

For a leading semiconductor chip maker

Client

The client is one of the world’s largest and highly valued semiconductor chip maker in the US.

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Expectation

The client wanted team Cientra to design and implement their chip and block level physical design. They wanted our team to take end-to-end ownership, from RTL to GDS.

Team

It was a 3-member physical design team, with consultative touch points from the senior management.

Duration

From RTL to GDS, the project was completed within a time frame of 8 months.

ROLES & RESPONSIBILITIES

The 3-member Cientra team successfully executed logic/physical synthesis, equivalence checking, physical design Implementation, IR analysis. They also:

  • Made possible
    the 28nm Full Chip/ Block implementation
  • Executed timing closure,
    physical verification
  • Handle complexity in terms of size
    (> 2 million instances) & frequency (>1GHZ)

PROJECT SPECIFICATIONS

DESIGN CHALLENGES

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