Executed AMS verification of complex blocks and complete Server
for a leading computer/laptop/server products and technologies company
Our client is a world leader of computer/laptop/server products and technologies.
The client wanted us to deliver a physical layer (SERDES PHY) circuit design of high speed interconnect IO/PLL for large datacenter server chipset.
A team of 3 MSV engineers were engaged in this project execution.
The team took 9 months to one week each to execute the blocks.
ROLES & RESPONSIBILITIES
Our team took complete ownership of BMOD (behavioral model) of blocks for TX/RX/Analog and High Speed monitoring. They also:
- Defined test cases for RTL team
to get the test, verifying it using RTL simulation
- Created AMS test using BMOD or Spice as per requirement,
defining forces where required, selecting voltage/current probes and finally running the simulation
- Realised satisfactory result analysis
with architecture, circuit and logics team
Synopsys XA/VCS, nWave and other waveform viewer, RTL simulator.
- Engagement Model
We followed a one-block-per person approach, with guidance from the management.
Targeted the analog/mixed-signal serial IO PHY for next generation datacenter server in a multi-CPU system.
- Design Spec
Speed up to 10.4 (Gen-I) and 11.2 (Gen-II) Gbps per channel and 20 channel system, in 28nm technology.
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