CASE STUDY

Enabled physical implementation of core for mobile chip

For a world leader of wireless and CDMA technologies

Client

Our client is a world leader of wireless and CDMA technologies.

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Expectation

The client wanted team Cientra to enable physical Implementation of Octa/Hexa/Quad CPU/GPU core for their mobile chip.

Team

An 8-member physical design team with support from senior management. Each member was engaged in handling up to 4 blocks.

Duration

The entire project was executed in 4 months.

ROLES & RESPONSIBILITIES

Team Cientra took complete ownership of netlist-to-GDSII, which comprised STA timing closure, reliability and physical verification sign-off. We also:

  • Precisely calculated and implemented
    – post base freeze – functional eco (or any other ECOs) with least disturbance in database, handling these manually
  • Actively contributed on all issues
    in flow and design, providing simple and portable solutions with least effort for end users
  • Engaged in verification of LEC and CLP
    for early identification of any issues, after every changes made in design

PROJECT SPECIFICATIONS

  • Tools
    Synopsys IC-compiler, PT-SI, Caliber, Cadence LEC and Cadence CLP
  • Engagement Model
    TNM, with a tape-out cycle of 3-4 months
  • Application
    Targeting the true 64 bit architecture for advanced cell phone chips with different processors for different market segments
  • Design Specs
    Speed up to 1.7GHz, with 20nm technology, blocks upto ~ 8mm2 with 180-200 memories/macros & 7-8 power domains

DESIGN CHALLENGES

  • Power domain aware
    CPF/UPF enabled floorplan/placement
  • Complex iterations for CTS/Routing
    for design closure with minimal number of metal layers
  • Excessive non default routing
    for extremely aggressive yield targets

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