Designed RF transceiver Circuit
for a leading mobile and wireless major
Our client is a leader in communication/ signal-processing/ sensor tech.
Our client had IP’s designed to meet the needs of different customers – leaders in communication/ signal-processing/ sensor tech. They wanted our help in designing their RF transceiver Circuits for mobile and wireless handheld devices.
Team of 17 resources were dedicated to this project: 2 architects, 6 circuit designers, 6 layout persons and 3 MSV resources.
The team took 24 months to execute this project.
ROLES & RESPONSIBILITIES
Our team developed high performance RFIC blocks for mm-wave transceivers using Cadence tools such as LNA, Mixer, RF-PLL, Filter, etc. We were able to:
- Understand RF/mm-wave transceiver specifications
and translate them into circuit-level specifications
- Design and verify calibration algorithms
such as DC cancelation, VCO setting, LO rejection, IQ gain and phase mismatch
- Execute physical layout of all circuits
and have a thorough understanding of all RF-layout requirements
- Participate in IC assembly,
SOC verification and lab evaluation
- Prepare and maintain project doc
including general spec & circuit description
Cadence virtuoso schematic editor, ADE-L/XL and Spectre/SpectreRF, ADS and HFSS.
- Engagement Model
We took complete ownership of the block from specs to GDS delivery with all functional and performance simulation qualifying the spec.
Targeting the analog/RF front end for next generation wireless communication system.
- Design Spec
Speed/Frequency like 800M-900MHz, 2.4/5GHz and multi-channel wireless system, in 90nm/65nm RF process technology.
- High-frequency front end
LNA, PA, modulator, mixer, LC-VCO, frequency divider/multiplier, switch, filter and phase shifter.
- Low jitter and phase noise LC-PLL (Local Oscillator)
driving clock to RF mixer and externally divided clock to I-Q mixer.
- Design of the power pad
had the same significant effects on the RF PA operation.
- General PA design challenges
such as low breakdown voltage, limited gain, parasitic cap and resistances, less power efficiency were also experienced
- LNA design was challenged by factors
such as impedance matching, power constrained noise matching, maintaining moderate to high gain over fairly large bandwidth, low power consumption, good linearity etc
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