Delivered physical layer circuit design of high speed interconnect IO/PLL
for a leading computer/laptop/server products and technologies company
Our client is a world leader of computer/laptop/server products and technologies.
The client wanted us to deliver a physical layer (SERDES PHY) circuit design of high speed interconnect IO/PLL for large datacenter server chipset.
A team of 2 circuit designers for each section (such as TX, RX, PLL+BG+ LDO+ Misc), 6 Layouts and 3 MSV resources were engaged in this requirement.
The team took one week each to execute the blocks.
ROLES & RESPONSIBILITIES
Our team took complete ownership of blocks from spec to post-layout, alongside the execution of functional and timing simulations:
- Performed layout review with signal /power RV cleaning
including ageing/burning characterization, timing violation report check, and identification and fix of issues ahead of final delivery
- Executed MSV simulation using Synopsys XA/VCS,
with complete power supply ramp and control voltages up/down
- BMOD (Behavioral Model) development
of respective blocks
- The team was part of the silicon characterization process –
starting from complete Power ON to detailed block level bench testing
Cadence virtuoso design editor, ADE-L/XL and Spectre / SpectreRF, Synopsys VCS/XA
- Engagement Model
End-to-end ownership – from specs to GDS delivery with all functional and timing simulation, qualifying the specification
Targeted the analog/mixed-signal serial IO PHY for next generation datacenter server in a multi-CPU system
We were able to deliver a speed of up to 10.4 (Gen-I) and 11.2 (Gen-II) Gbps per channel and 20 channel system with 28nm technology, current mode differential driver, 8-tap adaptive DFE, one LC-PLL driving clocks across all channels and on-chip LDO
- Low jitter and phase noise LC-PLL driving clock to serialize parallel data
- Current mode differential driver with programmable de-emphasis and on die termination resistance calibration
- CTLE peaking gain and bandwidth programmability achievement across all PVT
- 8 tap adaptive Decision feedback equalizer and Phase Interpolator based CDR for clock and data recovery
- 30 dB PSRR LDO with tight area limited decap
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