CASE STUDY

Delivered chip & block level physical design end-to-end

For a leading mobile chip manufacturer

Client

The client is one of the world’s largest mobile processor chip manufacturer.

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Expectation

The client wanted team Cientra to design and implement chip and block level physical design, with complete ownership from Netlist to GDS. Design and implement their chip and block level physical design. They wanted our team to take end-to-end ownership, from RTL to GDS.

Team

An 8-member physical design team with support from senior management.

Duration

From RTL to GDS, the project was completed in an 8-month time period.

ROLES & RESPONSIBILITIES

The 8-member Cientra team enabled Top level Partitioning, Top/Block level PD Implementation with multiple voltage and Switchable Power domains.  They also:

  • Made possible the 10nm
    Full chip/ block level implementation
  • Performed successfully LEC/CLP checks
  • Ensured timing closure
    and physical verification
  • Handled feed-through paths challenges
    in different voltage domains, complex clock structure, balancing critical paths related to analog IPs

PROJECT SPECIFICATIONS

DESIGN CHALLENGES

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